The group is seeking an experienced layout and mask design engineer to work on layouts for integrated photonics, quantum computing, and other emerging integrated circuit technologies. These technologies will be fabricated both in-house and in foundry-available processes. The engineer will work in the Cadence environment, with which they should be fluent, and will have responsibility for the full layout project from basic layout cell creation to final tapeout. Key tasks will include coding layout pcells; writing technology files; and laying out devices, test structures, systems, and full mask reticles based on input from device and process designers. They will also be responsible for working with the layout team to update and maintain a device pcell library, and for implementing revision control standards and documenting layout changes. They will help in the implementation of DRC and LVS decks, and final masks are expected to be DRC and LVS clean, when DRC and LVS decks are available. Assignments will be somewhat complex in nature and judgement will be required in resolving moderately complex problems.
Lexington, MA
United States