A new ISA interface between the software program (quantum circuit) and hardware (generation of the gates). Designed as an extension to the RISC-V ISA. The design implementation relies on the basic functionalities of the conventional ISA, with a suitable combination of operations for future scalability and parallelism. Implemented using Hardware Description Languages (HDL). The ISA (processor) can be fully used with software support.
Technology Area
Computing
Description
Patent or Application Number
63/271,277
Lead Licensing Institution
Lawrence Berkeley National Laboratory
IP was generated with QSA funds
No
Point of Contact
Sebastian Ainslie
URL
https://ipo.lbl.gov/quantum-instruction-set-architecture-quasar/