A new ISA interface between the software program (quantum circuit) and hardware (generation of the gates). Designed as an extension to the RISC-V ISA. The design implementation relies on the basic functionalities of the conventional ISA, with a suitable combination of operations for future scalability and parallelism. Implemented using Hardware Description Languages (HDL). The ISA (processor) can be fully used with software support.
Patent or Application Number63/271,277
Lead Licensing InstitutionLawrence Berkeley National Laboratory
IP was generated with QSA fundsNo
Point of ContactSebastian Ainslie